Overview

With MAxPy, you are able to:

• Simulate Verilog VLSI designs (either RTL or gate-level) inside a Python environment, with cycle-accurate results.

• Generate variations for your circuit in an automated way.

• Explore the effect of using approximate arithmetic blocks in your circuit.

• Apply Approximate Computing techniques to optimize resources usage, like area, power and timing.

Check the following tutorials to learn how to use MAxPy! Examples are provided in different complexity levels. We recommend for the examples to be followed through the proposed order, but you can skip to any of them which fullfil your design needs.